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Guidelines for reliability testing on circuit level

  Mika Mört & Soile Sääski
  Tekniikka ja teollisuus 1/2022 • 37 s. • Sähköinen 
  ISBN 978-952-316-405-5 (pdf)
  Hinta: Free of charge
  Publications pdf-file
   
  This publication is intended as study material for wafer or die level reliability testing and electronics failure analysis. The contents are a part of dissemination activities of CHARM project, in which Lapland University of Applied Sciences is a project partner.

Miniaturisation of electronics leads to new kinds of fault possibilities in microelectronics. “Guidelines for reliability testing on circuit level” introduces test methods for ensuring wafer level reliability to support design and development of electronics. Guidance to failure analysis supports the development process with information of the root cause for failure, and how it can be prevented.

Challenging environments tolerant Smart systems for IoT and AI (CHARM) is an ECSEL JU project, where 37 partners from 10 countries develop IoT solutions to withstand harsh industrial environments. The project partners develop new condition monitoring technologies, new sensors, novel package solutions and new connectivity to surroundings, where currently available technologies are not able to perform. The results of the project aim beyond state-of-the-art for European value chain of electronics and IoT.

This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876362. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Finland, Austria, Belgium, Czechia, Germany, Italy, Latvia, Netherlands, Poland, Switzerland.